Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - FIFO VHDL

Search list

[assembly language] 11

Description:
Platform: | Size: 114688 | Author: 开开 | Hits:

[VHDL-FPGA-Verilog] fifo89

Description: 先进先出FIFO缓冲器，8位字宽，9位字深，很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Platform: | Size: 269312 | Author: gdfrg | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules.
Platform: | Size: 6144 | Author: mao | Hits:

[VHDL-FPGA-Verilog] FT2232H_USB_Core

Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput. For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf" Included: VHDL core, NIOS test application, PC test application
Platform: | Size: 6144 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] uart_EP3C16_FIFO

Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Platform: | Size: 6756352 | Author: 515666524 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 这是用VHDL设计的一个8*9阵列的D触发器组成FIFO（first in first out）-This is a VHDL design using an 8* 9 array of D flip-flop composed of FIFO (first in first out)
Platform: | Size: 9216 | Author: crossover | Hits:

[VHDL-FPGA-Verilog] FIFO24_CS8416[1]

Description: Fifo buffer vhdl code
Platform: | Size: 1024 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] vhdl-fifo

Description: vhdl 语言实现fifo功能模块 包含接口：clk、data_in、data_out-fifo use vhdl
Platform: | Size: 1024 | Author: 张树强 | Hits:

[VHDL-FPGA-Verilog] actel_FPGA_example_source

Description: actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
Platform: | Size: 4096 | Author: leo | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo in vhdl file code
Platform: | Size: 1024 | Author: motti | Hits:

[VHDL-FPGA-Verilog] FT245

Description: 在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
Platform: | Size: 1024 | Author: 欧阳飞 | Hits:

[VHDL-FPGA-Verilog] fifo_vhdl

Description: 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
Platform: | Size: 13312 | Author: 站长 | Hits:

[VHDL-FPGA-Verilog] General-memory-VHDL-code-library

Description: 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
Platform: | Size: 23552 | Author: 周鑫 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用vhdl语言实现对八位数据进行缓存的控制-With VHDL language implementation to eight of the data cache of control
Platform: | Size: 523264 | Author: avir | Hits:

[VHDL-FPGA-Verilog] Flag-of-asynchronous-FIFO

Description: Quartus平台，VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
Platform: | Size: 82944 | Author: | Hits:

[VHDL-FPGA-Verilog] EDA-experiments-based-on-VHDL

Description: 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
Platform: | Size: 4096 | Author: shi xin | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 基于VHDL语言的fpga 实现FIFO 源程序，经验证可用，开发环境Quartus -VHDL FPGA FIFO QUARTUS II
Platform: | Size: 4096 | Author: 谢家 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: Quartus下VHDL编写的一个FIFO模块，调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
Platform: | Size: 336896 | Author: voldemortqq | Hits:

[Other] FIFO

Description: vhdl code for first in first out
Platform: | Size: 1024 | Author: amma | Hits:

[OS program] FIFO

Description: a fifo designed in vhdl. this fifo is implemented in a different way, using access type.
Platform: | Size: 2048 | Author: mohandes | Hits:
« 1 2 ... 7 8 9 10 11 1213 14 15 16 17 18 »

CodeBus www.codebus.net